Xtest
Test Creation
The ConXscan Xtest tool provides users an opportunity to quickly develop detailed boundary scan test patterns. Using an intuitive GUI, imported netlists and BSDL files and numerous options throughout test development, Xtest provides a comprehensive and feature-rich test development platform without the cost and complexity of multiple options required in many competing boundary scan software products.
All test patterns are automatically generated using the Test Creation Wizard derived from imported schematic netlists and BSDL files. BSDL files can be stored in a file vault to reduce the reliance on internal libraries and the problems that can occur with outdated files. Xtest prompts the user to confirm component designations and allows for customer rules to be used specific to an individual CAD designer. Xtest also directs users to assign pin mapping to non-scannable components such as connectors, resistors and jumpers.
Comprehensive Analysis
Xtest provides a comprehensive analysis of all components, schematics and netlists relating to the DUT. This feature allows test engineers the ability to quickly and completely review all relevant details of their test platform prior to running it.
Upon review of all required components, Xtest provides a checklist with a clear review of all possible changes to the configured sections of the imported netlist. The user can then lock the project for test execution, provided Xtest does not detect any errors.
DUT Verification
The first step that Xtest takes is to verify that DUT matches the schematics of the previously created test platform selected by the test engineer. This is a basic check that saves time during production debug should problems arise. In addition, a user can edit the constraints that have been selected to, for example, avoid contention on any given bi-directional net. This feature is particularly useful in debug.
Test Generation
One of the most powerful features of Xtest is the ability to allow users to designate how extensive the VIT (Virtual Interconnect Test) and VCCT (Virtual Component Cluster Test) procedures are run. The VIT procedure can either be extensive or streamlined (i.e. Test all pins on IC simultaneously), depending on the user's needed trade-offs between test coverage and speed. Xtest provides a graphical representation of speed versus test coverage to assist with evaluating the possible trade-offs the ATP generates. Similarly, the VCCT procedure can be run in either compiled or interpreted mode. The compiled mode provides quick pass/fail review, ideal for production line set-ups. The interpreted mode provides exhaustive details of all test points, allowing debug technicians to quickly identify problems.
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